The trend in the design of integrated circuit chips is for ever smaller geometry sizes and increasingly faster switching times. To further improve system speed, bus widths have been expanded with additional parallel input and output lines. Each output pin on a chip has an output driver which provides a relatively large current in response to a weaker signal generated by the chip. As the load on the bus increases, higher current is provided by the output drivers.
Whenever a logic gate on a chip is switched, as for example a logic gate in an output driver, a transient change in the current is created as the load is charged or discharged. Such transient currents create voltage transients in the power or ground path of the chip. The magnitude of voltage transients increases with increased bus width as additional drivers switch at the same time. Similarly, voltage transients increase as a result of the higher current required to drive larger loads.
Logic gates on the same chip, which share the power or ground paths of the output drivers, are known to switch logic states in response to such power or ground path voltage transients. This creates problems for both output and input drivers. For example, a ground transient or "bounce" can cause a high input to be erroneously recognized as a low level by an input buffer of a chip. An input buffer includes an inverter with series connected pull-up and pull-down transistors. The pull-down transistor has its gate connected to the high input and its source connected to ground. When the ground plane is steady, the gate-to-source voltage is (V.sub.GS) is large enough to keep the pull-down transistor "on" which keeps the output low. However, the inverter shares a common ground plane with the output drivers on the same chip. If the ground plane bounces as a result of one or more of the outputs switching, V.sub.GS decreases, turning off the pull-down transistor, and erroneously switching the output of the inverter. A similar result occurs for the pull-up transistor as a result of a voltage transient on the power supply.
In the past, attempts to prevent the problems associated with power and ground bounce have concentrated on limiting the magnitude of the voltage transient. A typical method of reducing the voltage transient is to slow the rate at which nodes switch. A disadvantage of this approach is that it increases somewhat the propagation delays through an input/output buffer and pad driver. Furthermore, as chips become faster, input buffers become increasingly sensitive to smaller voltage transients. Further reduction of the magnitude of the voltage transient would considerably increase propagation delays through the input/output buffer and pad driver.